SPI device configuration. More...

#include <idfxx_spi/include/idfxx/spi/master.hpp>

Public Attributes
uint8_t	command_bits = 0
	Default command phase length in bits (0-16).

uint8_t	address_bits = 0
	Default address phase length in bits (0-64).

uint8_t	dummy_bits = 0
	Dummy bits between address and data phase.

uint8_t	mode = 0
	SPI mode (0-3): (CPOL, CPHA) pair.

uint16_t	duty_cycle_pos = 0
	Duty cycle of positive clock in 1/256 increments (128 = 50%, 0 = default).

uint16_t	cs_ena_pretrans = 0
	SPI bit-cycles CS is active before transmission (half-duplex only).

uint8_t	cs_ena_posttrans = 0
	SPI bit-cycles CS stays active after transmission.

freq::hertz	clock_speed {0}
	SPI clock speed in Hz.

std::chrono::nanoseconds	input_delay {0}
	Maximum data valid time of slave.

idfxx::gpio	cs = gpio::nc()
	GPIO pin for chip select, or gpio::nc() if not used.

idfxx::flags< device_flags >	flags = {}
	Device capability flags.

int	queue_size = 1
	Transaction queue depth for async API.

Detailed Description

SPI device configuration.

Example:: spi::master_device device(bus, {

.mode = 0,

.clock_speed = 1_MHz,

.cs = idfxx::gpio_5,

.queue_size = 3,

});

idfxx::spi::master_device
A device on a SPI master bus.
Definition master.hpp:332

idfxx::spi::master_device::bus
master_bus & bus() const
Returns the parent bus.
Definition master.hpp:422

idfxx::gpio_5
constexpr gpio gpio_5
Definition gpio.hpp:895

idfxx::result
std::expected< T, std::error_code > result
result type wrapping a value or error code.
Definition error.hpp:120

Definition at line 347 of file master.hpp.

Member Data Documentation

◆ address_bits

uint8_t idfxx::spi::master_device::config::address_bits = 0

Default address phase length in bits (0-64).

Definition at line 349 of file master.hpp.

◆ clock_speed

freq::hertz idfxx::spi::master_device::config::clock_speed {0}

SPI clock speed in Hz.

Definition at line 355 of file master.hpp.

◆ command_bits

uint8_t idfxx::spi::master_device::config::command_bits = 0

Default command phase length in bits (0-16).

Definition at line 348 of file master.hpp.

◆ cs

idfxx::gpio idfxx::spi::master_device::config::cs = gpio::nc()

GPIO pin for chip select, or gpio::nc() if not used.

Definition at line 357 of file master.hpp.

◆ cs_ena_posttrans

uint8_t idfxx::spi::master_device::config::cs_ena_posttrans = 0

SPI bit-cycles CS stays active after transmission.

Definition at line 354 of file master.hpp.

◆ cs_ena_pretrans

uint16_t idfxx::spi::master_device::config::cs_ena_pretrans = 0

SPI bit-cycles CS is active before transmission (half-duplex only).

Definition at line 353 of file master.hpp.

◆ dummy_bits

uint8_t idfxx::spi::master_device::config::dummy_bits = 0

Dummy bits between address and data phase.

Definition at line 350 of file master.hpp.

◆ duty_cycle_pos

uint16_t idfxx::spi::master_device::config::duty_cycle_pos = 0

Duty cycle of positive clock in 1/256 increments (128 = 50%, 0 = default).

Definition at line 352 of file master.hpp.

◆ flags

idfxx::flags<device_flags> idfxx::spi::master_device::config::flags = {}

Device capability flags.

Definition at line 358 of file master.hpp.

◆ input_delay

std::chrono::nanoseconds idfxx::spi::master_device::config::input_delay {0}

Maximum data valid time of slave.

Definition at line 356 of file master.hpp.

◆ mode

uint8_t idfxx::spi::master_device::config::mode = 0

SPI mode (0-3): (CPOL, CPHA) pair.

Definition at line 351 of file master.hpp.

◆ queue_size

int idfxx::spi::master_device::config::queue_size = 1

Transaction queue depth for async API.

Definition at line 359 of file master.hpp.

The documentation for this struct was generated from the following file:

idfxx_spi/include/idfxx/spi/master.hpp

Public Attributes